The present invention relates to an operational amplifier circuit.
In recent electronic circuit design, there has been a demand for a lower supply voltage to reduce power consumption and noise. Designing an operational amplifier for such an electronic circuit to operate on a lower supply voltage inevitably results in a narrower input voltage range. In this respect, there is a demand for an operational amplifier capable of widening the input voltage range from the voltage of a high-potential power supply to the voltage of a low-potential power supply.
FIG. 1 shows a conventional operational amplifier 50. This operational amplifier 50, which is a voltage follower type, has an output terminal connected to an inverting input terminal (negative input terminal) to which an output signal OUT0 is applied as an input signal IN12. A high-potential supply voltage V.sub.CC (5 V) and a low-potential supply voltage V.sub.SS (0 V) are supplied to the operational amplifier 50 as its operational supply voltages.
FIG. 2 illustrates the practical internal circuit of the conventional operational amplifier 50. The operational amplifier 50 comprises a differential amplifier 51 with an MOS transistor structure and an inverting amplifier 53, which is comprised of complementary transistors. The differential amplifier 51 has two nMOS transistors T21 and T22, two pMOS transistors T23 and T24, and a constant current source 52.
The pMOS transistors T23 and T24 have their sources connected to the high-potential power supply V.sub.CC (5 V) and their gates connected to the drain of the pMOS transistor T24. The pMOS transistors T23 and T24 form a current mirror circuit.
The drains of the nMOS transistors T21 and T22 are respectively connected to the drains of the pMOS transistors T23 and T24. The sources of the nMOS transistors T21 and T22 are connected together to the low-potential power supply V.sub.SS (0 V) via the constant current source 52. The gate of the nMOS transistor T21 corresponds to a non-inverting input terminal to which an input signal IN11 is input. The gate of the nMOS transistor T22 corresponds to an inverting input terminal to which the output signal OUT0 is supplied as the input signal IN12.
The differential amplifier 51 outputs a signal, which is the inverted signal of the potential difference between the first input signal IN11 and the second input signal IN12, from the drain of the nMOS transistor T21. When the potential of the input signal IN11 is higher than that of the input signal IN12, more current flows in the nMOS transistor T21 and less current flows in the nMOS transistor T22. As a result, the potential of the output signal of the differential amplifier 51 drops. When the potential of the input signal IN11 is lower than that of the input signal IN12, on the other hand, less current flows in the nMOS transistor T21 and more current flows in the nMOS transistor T22. Consequently, the potential of the output signal of the differential amplifier 51 is higher than that when the potential of the input signal IN11 is higher than that of the input signal IN12.
The high-potential supply voltage V.sub.CC (5 V) and the low-potential supply voltage V.sub.SS (0 V) are supplied to the inverting amplifier 53 as its operational supply voltages. The inverting amplifier 53 amplifies the output signal of the differential amplifier 51 in accordance with its amplification factor (A) and sends out the resultant signal as the output signal OUT0.
In the operational amplifier in FIG. 2, the threshold voltages Vth of the nMOS transistors T21 and T22 are each 1 V, and the voltage drop in the constant current source 52 is 0 V. The gate-source voltage V.sub.GS of the nMOS transistor T21 is 0.5 V. When 4.5 V, which is slightly lower than the high-potential supply voltage, is applied as the input signal IN11, for example, the nMOS transistors T21 and T22 are turned on, and the differential amplifier 51 operates properly causing 4.5 V to be output as the output signal OUT0.
When 0.5 V, which is slightly higher than the low-potential supply voltage, is applied as the input signal IN11, on the other hand, the nMOS transistors T21 and T22 are turned off because the input voltage is lower than the threshold voltage Vth. As a result, the differential amplifier 51 does not properly operate, so that 0.5 V cannot be output as the output signal OUT0. The operational amplifier in FIG. 2 cannot therefore widen the voltage range of the input signals IN11 and IN12 to substantially the same range as that of the supply voltages.
FIG. 3 illustrates another example of a conventional operational amplifier 50, which is constituted by MOS transistors. This operational amplifier 50 comprises a differential amplifier 55 and the same inverting amplifier 53 as used in the previously discussed operational amplifier. The differential amplifier 51 has two nMOS transistors T25 and T26, two pMOS transistors T27 and T28, and a constant current source 56.
The nMOS transistors T25 and T26 have their sources connected to the low-potential power supply V.sub.SS (0 V) and their gates connected to the drain of the nMOS transistor T26. The nMOS transistors T25 and T26 form a current mirror circuit.
The drains of the pMOS transistors T27 and T28 are connected to the drains of the nMOS transistors T25 and T26, respectively. The sources of the pMOS transistors T27 and T28 are connected together to the high-potential power supply V.sub.CC (5 V) via the constant current source 56. The gate of the pMOS transistor T27 corresponds to a non-inverting input terminal to which an input signal IN11 is input. The gate of the pMOS transistor T28 corresponds to an inverting input terminal to which the output signal OUT0 is supplied as the input signal IN12.
The differential amplifier 55 outputs a signal, which is the inverted signal of the potential difference between the first input signal IN11 and the second input signal IN12, from the drain of the pMOS transistor T27. When the potential of the input signal IN11 is higher than that of the input signal IN12, less current flows in the pMOS transistor T27 and more current flows in the pMOS transistor T28. As a result, the potential of the output signal of the differential amplifier 55 drops. When the potential of the input signal IN11 is lower than that of the input signal IN12, on the other hand, more current flows in the pMOS transistor T27 and less current flows in the pMOS transistor T28. Consequently, the potential of the output signal of the differential amplifier 55 is higher than that when the potential of the input signal IN11 is higher than that of the input signal IN12.
In the operational amplifier in FIG. 3, the threshold voltages Vth of the pMOS transistors T27 and T28 are each -1 V, and the voltage drop in the constant current source 56 is 0 V. When 0.5 V, which is higher than the low-potential supply voltage, is applied as the input signal IN11, for example, the pMOS transistors T27 and T28 are turned on, and the differential amplifier 55 operates properly causing 0.5 V to be output as the output signal OUT0.
When 4.5 V is applied as the input signal IN11, on the other hand, the pMOS transistors T27 and T28 are turned off because the input voltage is greater than the difference (4 V) between the absolute value of the high-potential supply voltage and the absolute value of the threshold voltage Vth. As a result, the differential amplifier 55 does not properly operate, so that 4.5 V cannot be output as the output signal OUT0. Therefore, the operational amplifier in FIG. 3 cannot widen the voltage range of the input signals IN11 and IN12 to substantially the same range as that of the supply voltages.
FIG. 4 shows another example of the prior art where the operational amplifier 50 in FIG. 1 is constituted of bipolar transistors. This operational amplifier 50 comprises a differential amplifier 60 and the same inverting amplifier 53 as discussed above. The differential amplifier 60 has two npn transistors Q21 and Q22, two pnp transistors Q23 and Q24, and a constant current source 61.
The pnp transistors Q23 and Q24 have their emitters connected to the high-potential power supply V.sub.CC (5 V) and their bases connected to the collector of the pnp transistor Q24. The pnp transistors Q23 and Q24 form a current mirror circuit.
The collectors of the npn transistors Q21 and Q22 are connected to the collectors of the pnp transistors Q23 and Q24, respectively. The emitters of the npn transistors Q21 and Q22 are connected together to the low-potential power supply V.sub.SS (0 V) via the constant current source 61. The base of the npn transistor Q21 corresponds to a non-inverting input terminal to which an input signal IN11 is input. The base of the npn transistor Q22 corresponds to an inverting input terminal to which the output signal OUT0 is supplied as the input signal IN12.
The differential amplifier 60 outputs a signal, which is the inverted signal of the potential difference between the first input signal IN11 and the second input signal IN12, from the collector of the npn transistor Q21. When the potential of the input signal IN11 is higher than that of the input signal IN12, more current flows in the npn transistor Q21 and less current flows in the npn transistor Q22. As a result, the potential of the output signal of the differential amplifier 60 drops. When the potential of the input signal IN11 is lower than that of the input signal IN12, on the other hand, less current flows in the npn transistor Q21 and more current flows in the npn transistor Q22. Consequently, the potential of the output signal of the differential amplifier 60 rises.
In the operational amplifier in FIG. 4, the base-emitter voltages Vbe of the npn transistors Q21 and Q22 are each 0.7 V, and the voltage drop in the constant current source 61 is 0 V. When 4.5 V is applied as the input signal IN11, for example, the npn transistors Q21 and Q22 are turned on, and the differential amplifier 60 properly operates causing 4.5 V to be output as the output signal OUT0.
When 0.5 V, which is greater than the low-potential supply voltage, is applied as the input signal IN11, on the other hand, the npn transistors Q21 and Q22 are turned off because the input voltage is lower than the base-emitter voltage Vbe. As a result, the differential amplifier 60 does not properly operate, so that 0.5 V cannot be output as the output signal OUT0. Therefore, the operational amplifier in FIG. 4 cannot widen the voltage range of the input signals IN11 and IN12 to substantially the same range as that of the supply voltages.
In the various types of conventional operational amplifiers 50, as apparent from the above, the voltage range of the input signals IN11 and IN12 cannot be set to range from the voltage of the high-potential power supply to the voltage of the low-potential power supply. This prevents a reduction in the supply voltages.
Some operational amplifiers are designed to set the voltage range of the input signals IN11 and IN12 to the same range as that of the supply voltages by forming the nMOS transistors T21 and T22 of the differential amplifier 51 with depletion type field effect transistors (FETs). The depletion type FETs however suffer a complex fabrication process, which makes it difficult to design the FETs into an IC. Designing the depletion type FETs into an IC leads to a cost increase.